Chip Develpoments
Our group is developing full custom chips since 1994 within the europractice initiative. Up to now, about 20 designs have been submitted and successfully tested. They vary from simple transistor test structures to full readout chips for silicon strip and pixel detectors. At the moment, we are working on 7 HP workstations with the CADENCE software using different technologies. This page lists the most important designs starting with the most recent submissions.
CIX 0.2
Submitted 04/2005 to AMS 0.35 µm.
Size: 23.3 mm², 295.000 transistors.
Second generation prototype ASIC for x-ray imaging using simultaneous photon counting and charge integrating readout.
CIX 0.19
submitted 03/2005 to AMS 0.35 µm.
Size: 2.4 mm²
This chip incorporates several structures in differential-current-mode logic as well as an LVDS output stage.It was used for some detailed measurements for CIX0.2
Compton(Abacus)
submitted 03/2005 to AMS 0.35 µm.
Size: 20.4 mm²
128 channel counting readout ASIC for a sillicon strip detector used in a Compton polarimeter. Each channel has a CSA with continuous reset, pole-zero cancellation, CR-RC shaper with variable shaping time from 100ns to 400ns, a comparator with a DAC to tune the comparator threshold and an asynchronous ripple counter
CURO2
Submitted 09/2003 to TSMC 0.25 µm.
Size: 20.3 mm²
CUrrent Read Out chip for a DEPFET silicon detector matrix. CURO2 performs the parallel readout of 128 channels. For every readout channel a regulated cascode input stage and a current memory cell is used. Hits are found by a comparison with a programmable threshold current.
CIX
Submitted 08/2003 to AMS 0.35 µm.
Size: 6.3 mm², 30530 transistors.
Test chip for x-ray imaging applaying a circuit architecture that allows simultaneous counting and integrating readout.
CMOS-Matrix
Submitted 04/2003 to AMS 0.35 µm.
Size: 23.0 mm², 65540 transistors.
CMOS based pixel chip that is used to test a complete DEPFET readout system. The CMOS-Matrix has 64x128 cells with every cell having a NWELL-PSUB photodiode and additional circuitry that generates an offset current and an illumination dependent current.
Switcher2
Submitted 09/2002 to AMS 0.8 µm HV.
Size: 22.0 mm², 21220 transistors.
The SWITCHER2 chip is a 2x64 channel high voltage multiplexer used to control the readout of a DEPFET silicon detector. A RAM on the chip is used to store the control sequence. Several chips can be daisy chained if more than 64 channels are to be addressed.
SILAB1B
Submitted 01/2002 to TSMC 0.25 µm.
Size: 5.77 mm², 58000 transistors.
Test chip for the DEPFET based vertex detector for TESLA. It includes high speed current sampling structures, a hit scanner and a current comparator.Care was taken in the design of the on-chip control logic to allow simple testing of the various blocks at high speed.
SILAB1A
Submitted 01/2002 to TSMC 0.25 µm.
Size: 5.28 mm², 18000 transistors.
This test chip contains several structures to measure transfer characteristics, capacitances and matching of PMOS and NMOS devices with different geometries. Functional blocks include logic test circuits and a charge sensitive preamplifier with feedback.
FE-I
Submitted 11/2001 to IBM 0.25 µm.
Size: 81.4 mm², 2450000 transistors.
Front end chip for the Atlas pixel detector, in collaboration with LBL Berkeley and CPPM Marseille. The chip consists of an array of 18x160 pixels of 400x50mm² size. Each pixel contains a charge sensitive amplifier, a discriminator with adjustable threshold and a digital time stamp readout. The hit data is buffered at the bottom of the chip until a trigger signal selects or discards them.
FAUST12
Submitted 8/99 to AMS 0.8 µm.
Size: 4.8 mm², 3100 transistors.
Analog test amplifiers for pixel readout and other test structures.
FE-D
Submitted 8/98 to DMILL 0.8 µm, BiCMOS.
Size: 81.4 mm², 730000 transistors.
Front end chip for the Atlas pixel detector, in collaboration with CPPM Marseille and LBL Berkeley.
FAUST11
Submitted 7/98 to AMS 0.8 µm.
Size: 6.1 mm², 2400 transistors.
Analog test circuits like voltage references, a charge pump, buffer amplifiers, charge sensitive amplifiers, discriminators.
FE-C
Submitted 4/98 to AMS 0.8 µm.
Size: 81.4 mm², 892000 transistors.
FE-A (PIRATE)
Submitted 10/97 to AMS 0.8 µm, BiCMOS.
Size: 81.4 mm², 880000 transistors.
Pixel readout chips for ATLAS with full data sparsification logic in collaboration with CPPM Marseille. The second submission FEC is very similar to FEA but does not need the bipolar transistor.
CARLOS2.0
Submitted 7/01 to AMS 0.8 µm.
Size: 16.2 mm², 140000 transistors.
CARLOS1.1
Submitted 7/98 to AMS 0.8 µm.
Size: 6.5 mm², 4400 transistors.
CARLOS1.0
Submitted 12/97 to AMS 0.8 µm.
Size: 5.9 mm², 700 transistors.
A 64 channel low noise current to current amplifier for pulsed clear DEPJFET matrix (64x64 pixel) with track and hold and one fast serial output.
SWITCHER1.1
Submitted 7/99 to AMS 2.0 µm, HVCMOS.
Size: 23.8 mm².
SWITCHER1.0
Submitted 3/97 to AMS 2.0 µm, HVCMOS.
Size: 23.8 mm².
A 64 channel high voltage output chip to select and/or clear a single row of a pulsed clear DEPFET matrix.
MPEC2.2
Submitted 9/00 to AMS 0.8 µm.
Size: 41.6 mm², 429000 transistors.
MPEC2.1
Submitted 8/99 to AMS 0.8 µm.
Size: 48.7 mm², 400000 transistors.
MPEC2.0
Submitted 11/98 to AMS 0.8 µm.
Size: 14 mm², 59000 transistors.
MPEC1.???
Submitted 6/98 to AMS 0.8 µm.
Size: 23.2 mm², 159000 transistors.
MPEC1.???
Submitted 2/97 to AMS 0.8 µm.
Size: 22.1 mm², 147000 transistors.
These are counting pixel readout chip for imaging applications.
BIER51
Submitted 4/96 to AMS 0.8 µm, BiCMOS.
Size: 30 mm², 150000 transistors.
A pixel readout chip for ATLAS in collaboration with CPPMarseille.
MEPHISTO
Submitted 6/96 to AMS 0.8 µm.
Size: 11 mm², 61000 transistors.
A prototype of a digital 128 channel front end chip for silicon strip detectors with real time data sparsification and on chip data buffering.
FAUST10.1
Submitted 4/99 to Mietec 2.0 µm.
Size: 20.5 mm², 26600 transistors.
FAUST10.0
Submitted 4/96 to Mietec 2.0 µm.
Size: 19 mm², 6850 transistors.
A programable 128 channel multiplexer to read out silicon strip front end chips in applications without external trigger signals.
FAUST7
A 128 channel counter which uses linear feedback shift registers as counting elements. More info can be found in the paper 'An area efficient 128 channel counter chip'.
FAUST6
A readout buffer for the continuous DEPJFET detector.
The right image shows the needle test of FAUST6 on a probe station.
FAUST4
A self adjusting delay circuit (tunedelay) for use in pixel readout chips. Results can be found in the paper by P.Fischer and A. Joens: 'A self adjustment technique minimizing channel to channel variations in VLSI readout chips'.
FAUST2
Submitted to Mietec 2.4µm.
An analog four quadrant multiplier for use in a readout chip for silicon strip detectors.
FAUST1b
Submitted to Mietec 2.4µm.
Simple test structures (transistors, current mirrors, differential pair, etc...). They have been characterized in great detail in order to verify the simulations and to test different transistor models. Some results can be found in the Thesis of Andrea Jöns who was our first student doing chip design.
FAUST1a
Submitted to Mietec 2.4µm.
A pseudo random noise generator done in standard cell design. This was the first design we submitted after having installed the cadence software. The fully synchronous design operates correctly at a frequency of 60 MHz.